As the speed and degree of integration of semiconductor devices have been increased, the feature size of transistors has been reduced.
In a complementary metal oxide semiconductor (CMOS) device, which is a type of semiconductor devices, two types of transistors, i.e., an n-channel MOS (NMOS) transistor and a p-channel MOS (PMOS) transistor are used. In the NMOS transistor, on/off of current is controlled by transfer of electrons, and in the PMOS transistor, on/off of current is controlled by transfer of holes.
Conventionally, a gate insulating film used in a CMOS device is made of a silicon dioxide film, in general, and has a dielectric constant of about 3.9. However, when a gate insulating film has a reduced thickness since the size of transistors has been reduced, a leakage current is increased, and the power consumption and standby power consumption of the device are increased. Thus, the development of a high-k (high dielectric) gate insulating film has been conducted to allow reduction in equivalent oxide thickness (EOT) of the high-k gate insulating film even when an actual thickness of the high-k gate insulating film is larger than that of a silicon oxide film, using a gate insulating film having a dielectric constant of 4.0 or more.
However, if a conventional polysilicon gate electrode and a conventional high-k gate electrode are simply combined, a phenomenon called “depletion” of a gate electrode occurs. This is a phenomenon in which a depletion layer capacitance is generated between the high-k gate insulating film and the polysilicon gate electrode, thus eliminating the advantage that the EOT of the high dielectric gate insulating film is small. To reduce or prevent depletion of the gate electrode, it is necessary to combine a metal gate electrode, instead of the polysilicon gate electrode, with the high-k gate electrode. Furthermore, in forming a CMOS device, it is important to control a threshold voltage (Vt) at a proper level using the high-k gate insulating film/metal gate electrode.
When a conventional combination of a silicon oxide gate insulating film/a polysilicon gate electrode is used, an impurity such as boron and phosphorous, etc. is ion-implanted into polysilicon, and thermal treatment is performed to activate the impurity, thus improving the work function of polysilicon. For example, when polysilicon is not doped with an impurity, the work function of polysilicon is 4.65 eV, but the work function can be increased up to 5.15 eV by ion-implanting boron into polysilicon. By using this technique, threshold voltages Vt of a NMOS and a PMOS can be controlled.
However, when a high-k gate insulating film is used, due to traps contained in high density in the high-k gate insulating film, the Fermi level pinning which is a phenomenon in which the Fermi level is fixed occurs. Therefore, the work function cannot be changed at a doping level achieved by ion implantation, and threshold voltages cannot be controlled. Furthermore, in a metal-inserted-poly-Si stack (MIPS) structure including a combination of a metal gate electrode and a polysilicon gate electrode, it is difficult to adjust the work function by ion implantation, and the work function of a metal used for a gate electrode is dominant in Vt control.
In studies of the work function in such a combination of a high-k gate insulating film and a metal gate electrode, nitride of titanium, tungsten, tantalum, or molybdenum is used. As a metal gate electrode material, specifically, nitride of titanium and nitride of tungsten, each of which is nitride conventionally used as a DRAM material, are easy to handle in view of processing characteristics of dry etching and wet etching, etc.